A known approach for forming N/P doped fins involves depositing a thin film of boron/phosphorous (B/P) doped materials, e.g., phospho-silicate glass (PSG) and boro-silicate glass (BSG), over n-type metal-oxide-semiconductor (NMOS) and p-type metal-oxide-semiconductor (PMOS) fins, respectively, and then driving the dopants into the fin sidewalls by annealing. Adverting to FIG. 1 (a two-dimensional (2D) cross-sectional view), n-type fins 101 and p-type fins 103 are formed by depositing an in-situ steam generation (ISSG) or pad oxide layer 105 over the silicon (Si) pillars 107 formed on a Si substrate 109. The ISSG or pad oxide layer 105 is then removed from an upper surface of the Si pillars 107. Next, a nitride cap 111 is formed on the upper surface of the Si pillars 107 and an oxide cap 113 is formed on an upper surface of the nitride cap 111. A PSG layer 115 is conformally deposited, e.g., to a thickness of 3 nm to 5 nm, over the n-type and p-type fins 101 and 103, respectively, by chemical vapor deposition (CVD). Next, a nitride layer (not shown for illustrative convenience) is conformally deposited, e.g., to a thickness of 0.8 nm to 3.5 nm, over the PSG layer 115 by atomic layer deposition (ALD) or furnace deposition.
Adverting to FIG. 2, an integrated nitride reactive-ion etching (RIE) and a PSG RIE spacer etch are performed. The integrated etch process removes the nitride layer, ISSG or pad oxide layer 105, and PSG layer 115 from on top of and between the n-type fins 101 and p-type fins 103, as well as the oxide cap 113 on each fin. A lithography stack 301, including a spin-on-hardmask (SOH) layer 303, a silicon oxynitride (SiON) layer 305, a buried anti-reflective coating (BARC) layer 307, and photoresist 309, is then formed over the n-type fins 101 and p-type fins 103, and the BARC layer 307 and the photoresist 309 are removed, as depicted in FIG. 3. Adverting to FIG. 4, the lithography stack 301 is opened onto the p-type fins 103. An n-type well (n-well) implant is then performed by implanting phosphorous/arsenic (P/As) into the substrate 109. Next, an integrated nitride spacer SiCoNi™ etch selective to the PSG layer 115 and a PSG spacer (and ISSG or pad oxide) SiCoNi™ etch (both not shown for illustrative convenience) are performed exposing the p-type fins 103, as depicted in FIG. 5. The remainder of the lithography stack 301 is then removed from over the n-type fins 101.
Adverting to FIG. 6, a BSG layer 601, is deposited, e.g., to a thickness of 3 nm to 5 nm, over the n-type and p-type fins 101 and 103, respectively, by chemical vapor deposition (CVD). The BSG layer 601 may pile up in between the n-type fins 101, and the BSG layer 601 is in contact with the p-type fins 103. In contrast, the PSG layer 115 is formed over the ISSG or pad oxide layer 105, which is formed over the Si pillars 107, with respect to the n-type fins 101. Next, a spacer etch back is performed on the BSG layer 601 by RIE, removing approximately 5 nm of the BSG layer 601, as depicted in FIG. 7. The expectation is that since phosphorous diffuses faster than boron, solid state diffusion of phosphorous from PSG can happen through the ISSG or pad oxide layer 105.
Next, a lithography stack 801, including a SOH layer 803, a SiON layer 805, a BARC layer 807, and photoresist 809, is formed over the n-type and p-type fins 101 and 103, respectively, as depicted in FIG. 8. Adverting to FIG. 9, a portion of the lithography stack 801 is removed exposing the n-type fins 101 and the photoresist 809 and the BARC layer 807 are removed. The BSG layer 601 is then etched from the n-type fins 101, e.g., by SiCoNi™, as depicted in FIG. 10. The remainder of lithography stack 801 is then removed. Adverting to FIG. 11, a nitride layer 1101 is deposited over both the n-type and p-type fins 101 and 103, respectively, and the substrate 109. As a result of the n-type fins already having a nitride layer (not shown for illustrative convenience), the total nitride thickness over the n-type fins 101 is much thicker than the nitride layer 1101 formed over the p-type fins 103.
Adverting to FIG. 12, a shallow trench isolation (STI) layer 1201 is formed over the nitride layer 1101. The STI layer 1201 is then planarized, for example, by CMP, down to the upper surface of the Si pillars 107, removing the nitride cap 111. The STI layer 1201 is then recessed 38 nm to 44 nm to expose a portion of the n-type and p-type fins 101 and 103, respectively, as depicted in FIG. 13. The portions of the ISSG or pad oxide layer 105, the PSG layer 115, the BSG layer 601, the nitride layer (not shown for illustrative convenience), and the nitride layer 1101 exposed by the recessed STI layer 1201 are then stripped down to the Si pillars 107. Thereafter, the dopants are driven into the n-type and p-type fins 101 and 103, respectively, using a high temperature anneal process.
Another known approach involves a similar process flow with boron/phospho-silicate glass (B/PSG) doping thin film magnetodielectric (TFM) layers on PMOS and NMOS fins. However, these approaches can require numerous complicated B/PSG deposition and masking steps; lack easy to control dopant profiles; and may cause implant damage/leakage and, therefore, device defectiveness.
A need therefore exists for methodology enabling the introduction of N/P dopants in silicon and the dopants to be driven into the fin areas at the SSRW layer without complicated processing or implant damage/leakage and the resulting device.